The present invention relates generally to split-gate p-channel Electrically Erasable Programmable Read Only Memory (EEPROM) cells, and more particularly to a split-gate memory cell having select and memory transistors that share an active channel region and have independent and distinct threshold voltage (Vt) adjusts that optimize the programming window of the memory cell.
EEPROM memory cells are a class of nonvolatile semiconductor memory in which information may be electronically programmed into and erased from each memory element or cell. Split-gate EEPROM memory cells are one type of EEPROM cell in which the select and memory transistors are merged so that they share the same polysilicon gate, commonly known as the poly 2 or select gate. The poly 2 gate forms both the wordline or gate electrode of the select transistor and the control gate of the memory transistor. This configuration allows for a smaller cell size and thus provides a more efficient design.
Information is stored in split-gate EEPROM memory cells by placing electronic charge on a xe2x80x9cfloating gatexe2x80x9d, which is typically a region of conductive polysilicon (commonly known as poly 1) that is electrically isolated from other conducting regions of the device by insulating dielectric layers that surround it. The charge on the floating gate can be detected in reading the memory cell because it changes the threshold voltage of the memory transistor. This change in threshold voltage changes the amount of current that flows through the cell when voltages are applied to it during the read operation and the current can be detected by a sense amplifier circuit.
In a typical EEPROM design, n-channel cells are produced over a p-well substrate. In U.S. Pat. No. 5,790,455 entitled xe2x80x9cLow Voltage Single Supply CMOS Electrically Erasable Read-Only Memoryxe2x80x9d, which is issued to Caywood and licensed to the assignee of the present application and incorporated herein by reference, however, the opposite configuration is described, namely, p-channel devices over an n-well, which itself resides in a p-type substrate. The advantage of this configuration is that it reduces the magnitude of the applied voltage required for erasing and writing to the device, while maintaining a similar writing speed as compared to the prior art. This configuration also eliminates certain components functionally necessary in the prior art.
Referring to FIG. 1, the Caywood approach is illustrated in general terms for a single memory transistor 1. The n-well 3 is created within a p-type substrate 2 and the p-type diffusion regions for the source 4 and drain 5 is created within the n-well 3. Thus, in this design, the select and memory transistors share a common active channel region. The poly 1 or floating gate 6 of the memory transistor 1 is created after the active region for the source 4 and drain 5. The poly 2 or select gate 7 of the memory transistor 1 is fabricated over the floating gate 6. Various non-conductive layers 8 (not shown) insulate the source 4 and drain 5, the floating gate 6 and the select gate 7 from each other.
In the Caywood approach and other prior p-channel designs, the channels of both the memory cell and select transistors are embedded with the same threshold voltage adjust implants or adjusts. The threshold voltage adjust in these devices is used to set the threshold voltage of the select transistor to its desired value. The threshold voltage of the memory transistor, however, is not set to any value, but rather assumes a xe2x80x9cnaturalxe2x80x9d Vt value (zero charge on the floating gate). The drawback of this solution is that when the p-channel memory transistor is xe2x80x9cprogrammedxe2x80x9d into the conductive state, its threshold voltage can be much more positive than the select transistor. In this case, the threshold voltage of the select transistor alone controls the combined threshold voltage of the memory transistor and select transistor. Thus, part of the threshold window (Vt window) of the cell, i.e., the difference between the threshold voltages of the cell in the programmed (Vtw) and the erased (Vte) states, is lost.
For example, the memory cell transistor alone might have a programmed Vt of +3.0 V (volts) and an erased Vt of xe2x88x925.0 V, while the select transistor would typically have its Vt set at xe2x88x920.8 V. The overall threshold window of the memory cell and select gate would be from xe2x88x920.8 V to xe2x88x925.0 V, and not the threshold window of the memory cell alone which is from +3.0 V to xe2x88x925.0 V. The part of the threshold window from +3.0 V to xe2x88x920.8 V is lost. The disadvantage of this is that it reduces the working life of the memory cell.
In particular, the Vt window of a cell changes with the number of program and erase cycles that it undergoes. The Vt window typically collapses with increasing program/erase cycles due to electron trapping in the tunnel oxide. FIG. 2 illustrates for a p-channel split-gate EEPROM cell how the Vt window decreases with cycles. The solid lines for Vtw and Vte indicate the average values of the thresholds of a large population of cells. The dashed lines on either side indicate the spread in Vtw and Vte due to processing variations. In addition to the process variations and Vt window collapse with program/erase cycling, some loss of charge with time from an erased or written cell must also be accounted for. This is indicated as an inner pair of dotted lines, which reduces the minimum Vt window even more. The minimum Vt window at any given number of cycles is taken inside the dotted line envelope. Beyond all of this, there are still other effects, such as a sense amplifier trip point variations and variations due to operation over a range of temperatures, that require that the VT window be made even wider.
There are a number of ways of increasing the Vt window, but they all have drawbacks. For example, the Vt window can be made wider by using a larger programming voltage, Vpp. However, if Vpp is increased, then the tunnel oxide is subjected to a larger electric field stress in each program/erase cycle and the Vt window collapse with cycling becomes worse. The Vt window can also be made wider by making the tunnel oxide thinner. However, making the tunnel oxide thinner, makes it more likely that charge stored on the floating gate will leak off over time after the tunnel oxide has been stressed with program/erase cycles. This effect is known as stress-induced leakage current (SILC). The Vt window can further be widened by increasing the coupling ratio of the cell. An increase in the coupling ratio of the cell is possible only by either increasing the silicon chip area consumed by the cell or by decreasing the interpoly dielectric thickness. It is not desirable to increase the silicon chip area for obvious reasons, and decreasing the interpoly dielectric can also reduce the ability of the cell to retain charge, as well as make it more difficult to manufacture the cell in a high yielding process.
Accordingly, it is desirable to optimize the programming window of the memory cells in a p-channel split-gate EEPROM without any of the drawbacks associated with the solutions mentioned above.
In one aspect of the present invention, a split-gate EEPROM memory cell is provided. The memory cell includes a memory transistor and select transistor that share a common gate. The memory cell further includes two independent and distinct threshold voltage adjusts implanted in different portions of a channel region of substrate of the memory cell. One of the threshold voltage adjusts is disposed in relation to the memory transistor so as to influence its threshold voltage. The other threshold voltage adjust is disposed in relation to the select transistor so as to influence its threshold voltage. In the preferred embodiment of the present invention the threshold voltage adjust associated with the memory transistor is formed of an n-type dopant, preferably Arsenic or Phosphorus. In this embodiment, the threshold voltage adjust associated with the select transistor is formed of a p-type dopant, preferably Boron or BF2.
In another aspect of the present invention, a method of fabricating a split-gate memory cell is provided. The method includes the step of implanting a threshold voltage adjust associated with the memory transistor in a channel region of a substrate of the memory cell. The method further includes the step of implanting a threshold voltage adjust associated with the select transistor in a different portion of the channel region of the cell substrate. In the preferred method, the threshold voltage adjust associated with the memory transistor is formed by implanting an n-type dopant into the channel region of the substrate. In this method, the threshold voltage adjust associated with the select transistor is formed by implanting a p-type dopant into the channel region of the substrate. During this step, implantation of the p-type dopant in the portion of the channel region associated with the memory transistor is prevented by the floating gate, which acts as a self-aligning mask.
In one embodiment of the invention, the step of implanting the n-type of dopant is performed before the floating gate is formed. In another embodiment, this step is performed after the floating gate is formed.
The use of independent and distinct threshold voltage adjusts widens the threshold voltage window of the memory transistor and select transistor, and thus extends the operational life of the memory cell.